Page 1 of 5
Journal for Studies in Management and Planning
Available at http://edupediapublications.org/journals/index.php/JSMaP/
e-ISSN: 2395-0463
Volume 02 Issue 11
November 2016
Available online: http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 137
An Innovative Technology for Lowering the Power Dissipation in SOC
1. M Vijaya,2. Mr.P.V.Vara Prasad Rao
1
PG Scholar, Department of ECE, SLC's Institute of Engineering and Technology, Piglipur Village, Hayathnagar Mandal,
Near Ramoji Film City, Ranga Reddy District, Hyderabad, Telangana
2Assosciate Professor, Department of ECE, SLC's Institute of Engineering and Technology, Piglipur Village,
Hayathnagar Mandal, Near Ramoji Film City, Ranga Reddy District, Hyderabad, Telangana
ABSTRACT:
The suggested encoding schemes, that are transparent with regards to the router implementation,
are presented and talked about at both algorithmic level and also the architectural level, and
assessed by way of simulation on synthetic and real traffic situations. As technology decreases,
the ability dissipated through the links of the network-on-nick (NoC) begins to contend with the
ability dissipated through the additional factors from the communication subsystem, namely, the
routers and also the network connects (NIs). Global interconnect length doesn't scale with
smaller sized transistors and native wires. The network on-nick design paradigm is known as
probably the most viable method to tackle with scalability and variability problems that
characterize the ultra-deep sub-micron meter era. Within this paper, we present some data
encoding schemes targeted at lowering the power dissipated through the links of the NoC. The
suggested schemes are general and transparent with regards to the underlying NoC fabric. The
information encoding plan is yet another way in which was used to lessen the link power
dissipation. This group of encoding isn't appropriate to become used in the deep sub-micron- meter technology nodes in which the coupling capacitance comprises a main issue with the entire
interconnect capacitance.
Keywords: Coupling switching activity, data encoding, and interconnection on chip, low
power, network-on-chip (NoC), and power analysis.
I. INTRODUCTION
Nowadays, the on-nick communication
issues are as relevant as, and perhaps more
relevant than, the computation related issues
Within this paper, we concentrate on
techniques targeted at lowering the power
dissipated through the network links. Nick
size remains relatively constant since the
nick function is constantly on the increase
and RC delay increases tremendously [1].
Page 2 of 5
Journal for Studies in Management and Planning
Available at http://edupediapublications.org/journals/index.php/JSMaP/
e-ISSN: 2395-0463
Volume 02 Issue 11
November 2016
Available online: http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 138
When the raw computation horsepower
appears to become limitless, because of the
ability of instancing increasingly more cores
in one plastic die, scalability issues, because
of the necessity of making efficient and
reliable communication between your
growing quantity of cores, end up being the
real problem. Shifting from the plastic
technology node to another one leads to
faster and much more power efficient gates
but reduced and much more power hungry
wires. Global interconnect length doesn't
scale with smaller sized transistors and
native wires. The network on-nick design
paradigm is known as probably the most
viable method to tackle with scalability and
variability problems that characterize the
ultra-deep sub-micron meter era. Actually,
the ability dissipated through the network
links is really as relevant as that dissipated
by routers and network connects as well as
their contribution is anticipated to improve
as technology scales. Particularly, we
present some data encoding schemes
operating at flit level as well as on an finish- to-finish basis, which enables us to reduce
both switching activity and also the coupling
switching activity on links from the routing
pathways traversed through the packets.
Case study considers several aspects and
metrics from the design, including plastic
area, power dissipation, and consumption.
The suggested encoding schemes, that are
transparent with regards to the router
implementation, are presented and talked
about at both algorithmic level and also the
architectural level, and assessed by way of
simulation on synthetic and real traffic
situations.
II. PREVIOUS STUDY
During these chips, a substantial fraction
from the total system power finances is
dissipated by interconnection systems.
Therefore, the style of power-efficient
interconnection systems continues to be the
main focus of numerous works printed
within the literature coping with NoC
architectures. The information encoding
techniques might be classified into two
groups. Within the first category, encoding
techniques focus on decreasing the power
because of self-switching activity of person
bus lines while disregarding the ability
dissipation because of their coupling
switching activity [2]. These works focus on
different aspects of the interconnection
systems for example routers, NIs, and links.
Because the focus of the paper is on
lowering the power dissipated through the
links, within this section, we briefly review
a few of the works in link power reduction.
All of them boost the nick area. The
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Page 3 of 5
Journal for Studies in Management and Planning
Available at http://edupediapublications.org/journals/index.php/JSMaP/
e-ISSN: 2395-0463
Volume 02 Issue 11
November 2016
Available online: http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 139
information encoding plan is yet another
way in which was used to lessen the link
power dissipation. This group of encoding
isn't appropriate to become used in the deep
sub-micron-meter technology nodes in
which the coupling capacitance comprises a
main issue with the entire interconnect
capacitance. This will cause the ability
consumption because of the coupling
switching activity to become large fraction
from the total link power consumption,
making these techniques, which ignore such
contributions, inefficient. The switching
activity is reduced using many extra control
lines.
Fig.1. Circuit diagram of the Encoder
III. IMPLEMENTATION
The plan presented, worked with lowering
the coupling switching. Within this method,
an intricate encoder counts the amount of
Type I transitions having a weighting
coefficient of 1 and the amount of Type II
transitions using the weighting coefficient of
two. Finally, in Plan III, we think about it
that Type I transitions show different
behaviors within the situation of odd as well
as inverts making the inversion which
results in the greater power saving. A coding
technique that cuts down on the coupling
switching activity if you take the benefit of
finish-to-finish encoding for wormhole
switching continues to be presented. It is
dependent on decreasing the coupling
switching activity by getting rid of only
Type II transitions. Within this paper, we
present three encoding schemes. In Plan I,
we concentrate on reducing Type I
transitions during Plan II, both Types I and
II transitions are taken into consideration for
determining between half and full invert,
depending the quantity of switching
reduction. The fundamental concept of the
suggested approach is encoding the flits
prior to being injected in to the network with
the aim of minimizing the self-switching
activity and also the coupling switching
activity within the links traversed through
the flits. Actually, self-switching activity
and coupling switching activity have the
effect of link power dissipation. Within this
paper, we make reference to the finish-to- finish plan [3]. This finish-to-finish
encoding technique uses the pipeline nature
from the wormhole switching technique.
Observe that because the same sequence of
flits goes through all of the links from the
routing path, the encoding decision taken in
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