A Novel Method For Fault Coverage And Routing Path Delay Reduction In GDI Logic Design

Abstract

Small Delay Defects are introduced for high quality performance in the industry. Various ATPG tools will produce the timing information to select the longest path. In this paper, a novel method for fault coverage and routing path delay reduction in GDI logic design. Due to timing requirements in GDI design, the new scheme is introduced to detect the delay faults effectively. By extracting the common paths in the circuit, the number of nodes will be reduced. The fault coverage and routing path will perform its operation depend on the circuit. This system will propagate the faults by using routing procedure. Small delay defects will produce high fault coverage to overcome this routing procedure is introduced. The fault coverage and routing path delay design will reduce the low faults coverages compared to SDD. This system will exploit the characteristics of GDI circuitry to enable the applications of test pattern circuitry.